NVIDIA RTX Blackwell Architecture Explained: What Changed in the RTX 50 Series

What is new in the NVIDIA RTX Blackwell architecture?

RTX Blackwell keeps Ada's process node and reworks the parts around the shader core. The GeForce RTX 5090 and RTX 4090 are both built on TSMC 4N, so the gains come from a bigger die (750 mm² against 608.5 mm² for AD102), GDDR7, and new units for neural rendering ^[1]. The stated SM design goal: Ada was tuned for standard shaders, Blackwell for neural shaders ^[1].

Four cards launched first: the RTX 5090, 5080, 5070 Ti and 5070. The RTX 5090 and RTX 5080 went on sale on January 30, 2025, and the 5070 Ti and 5070 followed in February ^[2]. NVIDIA published the architecture whitepaper on January 28, 2025, and later revised it to v1.1 with notes on integer throughput and GDDR7 ECC ^[2][1].

How big are the GB202 and GB203 chips?

GB202 is the flagship die. The full chip has 92.2 billion transistors, 12 GPCs, 96 TPCs, 192 SMs and a 512-bit memory bus built from sixteen 32-bit controllers ^[1]. That adds up to 24,576 CUDA cores, 192 RT Cores, 768 Tensor Cores and 128 MB of L2 cache ^[1].

The RTX 5090 ships a cut-down GB202. Here it is against the RTX 4090, using NVIDIA's figures ^[1].

Spec	RTX 4090 (AD102)	RTX 5090 (GB202)
SMs	128	170
CUDA cores	16,384	21,760
Tensor Cores	512 (4th gen)	680 (5th gen)
Boost clock	2,520 MHz	2,407 MHz
Memory	24 GB GDDR6X, 21 Gbps	32 GB GDDR7, 28 Gbps
Bandwidth	1,008 GB/s	1,792 GB/s
L2 cache	72 MB	96 MB
TGP	450 W	575 W
Process	TSMC 4N	TSMC 4N

From those figures, the RTX 5090 has about 33% more SMs at a slightly lower boost clock, so its compute gain comes from width, not frequency ^[1]. Bandwidth rises by about 78%, and the larger L2 is aimed at ray tracing, path tracing in particular ^[1].

GB203, the chip behind the RTX 5080, has 45.6 billion transistors, 84 SMs, a 256-bit bus and 64 MB of L2 ^[1]. The RTX 5080 pairs it with 30 Gbps GDDR7 for 960 GB/s ^[1].

What changed inside the Blackwell SM?

Each SM still has 128 CUDA cores, one RT Core, four Tensor Cores, four texture units, a 256 KB register file and 128 KB of configurable L1 and shared memory ^[1]. The change is in how those 128 cores split their work.

On Ada, half the cores in an SM could run either FP32 or INT32, and the other half ran FP32 only. Blackwell makes all of them unified, which doubles the peak rate for many integer instructions ^[5][1]. Each unified core still runs either FP32 or INT32 in a given clock cycle, and not every integer operation reaches 2x ^[1].

The University of Delaware team that microbenchmarked an RTX 5080 flags the same limit as a potential hazard for mixed INT32 and FP32 workloads ^[3]. Treat 2x as a peak rate for integer-heavy code, not a promise for mixed kernels.

Why spend silicon on integers in a graphics chip? The whitepaper says the faster integer path speeds up address generation, which neural shading depends on ^[1]. ServeTheHome, covering NVIDIA's Hot Chips 2025 talk, links it to the sorting work behind Shader Execution Reordering ^[4].

The SM also doubles point-sampled texture throughput per clock, which speeds up the stochastic texture filtering used by Neural Texture Compression ^[1].

What do the fifth-generation Tensor Cores add?

They add FP4 and FP6 data types and a second-generation FP8 Transformer Engine, on top of the FP16, BF16, TF32, INT8 and FP8 support carried over ^[1]. FP4 needs less than half the memory of FP16, the precision most models ship in ^[1]. At Hot Chips 2025, the pitch was FP4 as accurate enough for graphics models while using half the memory and half the compute ^[4].

The whitepaper's example is Black Forest Labs' FLUX.dev, which needs more than 23 GB of VRAM at FP16 and less than 10 GB at FP4 ^[1]. A 30-step image takes 15 seconds on an RTX 4090 at FP16 and just over five seconds on an RTX 5090 at FP4 ^[1].

Read that as a precision change plus a hardware change, not a like-for-like speedup, since FP4 Tensor Core support is new in Blackwell ^[1].

For shader authors, the bigger change is access. With the Cooperative Vectors API for DirectX 12 and Vulkan, Tensor Cores can be called from any shader stage, including pixel and ray tracing shaders ^[1][5]. Until now, DLSS reached the Tensor Cores through CUDA ^[1].

One example in the whitepaper is neural texture compression, at up to seven-to-one VRAM compression over block-compressed formats ^[1].

How did the fourth-generation RT Cores change?

The RT Core doubles ray-triangle intersection throughput over Ada ^[1]. It also adds a Triangle Cluster Intersection Engine for Mega Geometry, and a new primitive, Linear Swept Spheres, for hair and other thin geometry ^[1].

Mega Geometry targets engines like Nanite that swap level of detail in clusters of about 128 triangles ^[1].

It adds cluster-level acceleration structures (CLAS), built from batches of up to 256 triangles and cached across frames. That cuts later BVH build work by two orders of magnitude, and a LOD switch rebuilds only the BVHs of affected objects ^[1]. The API runs on every RTX GPU back to Turing, through NVAPI for DXR, Vulkan vendor extensions and OptiX 9.0 ^[1]. Blackwell's RT Core adds cluster engines and geometry and BVH compression that speed it up further, which the whitepaper says trims several hundred MB of VRAM from typical Nanite scenes ^[1].

For hair on human characters, Linear Swept Spheres are about 2x faster than its earlier triangle-strip method (DOTS) and need about 5x less VRAM ^[1].

What is Shader Execution Reordering 2.0?

SER regroups divergent ray tracing threads so they run more coherently, which helps most in path tracing ^[1]. Blackwell's reorder logic is twice as efficient as Ada's, which lowers reorder overhead and improves precision ^[1]. Path-traced games and production renderers that already call the SER API get the gain without code changes ^[1]. Threads that run neural work can also be sent straight to the Tensor Cores ^[1].

What does the AI Management Processor do?

The AI Management Processor (AMP) is a dedicated RISC-V core at the front of the GPU pipeline that schedules GPU contexts instead of the CPU ^[1]. It follows Microsoft's Hardware-Accelerated GPU Scheduling model, introduced in the Windows 10 May 2020 Update ^[1].

The target workload is a game running alongside AI models for speech, vision or animation. For LLMs, AMP aims to cut time to first response; for games, it prioritizes engine work to avoid stutter ^[1]. Its Hot Chips talk framed this as interleaving graphics and ML without expensive context switches ^[4].

Why does GDDR7 use PAM3 instead of PAM4?

PAM3 sends 1.5 bits per cycle against PAM4's 2 bits, but its cleaner signal allows much higher clock speeds, which more than makes up the difference ^[1][4]. GDDR7 also doubles the number of independent channels ^[1].

For reliability, GDDR7 on GeForce RTX cards has on-die ECC that is always enabled. It corrects single-bit errors with no performance cost, NVIDIA says, so there is no toggle in the driver ^[1].

How does Blackwell manage power?

The whitepaper calls this the largest overhaul of the clock architecture in over a decade. Clocks can now change 1000x faster than on earlier GPUs, so frequency can move within a single frame instead of being held for the whole frame ^[1].

The memory clock tree can be fully gated for the first time, using GDDR7's fast wake-up ^[1]. A separate voltage rail now feeds the GPU cores and the memory system, so the chip can power down idle core regions at frame granularity, which mainly helps laptops ^[1]. TechPowerUp reports a 15x reduction in the time it takes to rail-gate the core ^[5].

What changed in video and display?

The ninth-generation NVENC and sixth-generation NVDEC add 4:2:2 hardware encode and decode for H.264 and HEVC, a format common in professional cameras ^[1]. NVDEC decodes H.264 twice as fast as before. The RTX 5090 carries three encoders and two decoders, which NVIDIA rates at over 50% faster video exports than the previous generation ^[1].

Display output moves to DisplayPort 2.1b with UHBR20, up to 80 Gbps ^[1]. That supports 8K at 165 Hz and 4K at 480 Hz, both with DSC, and the top link rates need a DP80LL-certified cable ^[1].

What should developers do with this?

Check whether your hot loops mix INT32 and FP32 work, because the unified cores lift Ada's half-the-cores limit on integer work but still run one type per clock ^[5][3]. Then look at Cooperative Vectors and FP4 for any neural pass you run per pixel; neither has an equivalent on Ada.